The present invention relates to a semiconductor apparatus, and more particularly to a semiconductor apparatus such that the electrical properties have been improved using thin wiring with a substantially symmetric wiring pattern with respect to the semiconductor chip, production is easy, and it is possible to improve heat radiation while being compact.
In recent years, accompanying a demand for more compact, higher performance electronic equipment, semiconductor apparatuses with multiple pins yet being compact have been sought through larger scale integration of semiconductor chips themselves. In addition, accompanying the demand for greater compactness and higher performance, greater compactness and higher performance of semiconductor apparatuses have been targeted by using multi-chip packages (MCPs) in which a plurality of semiconductor chips are arranged inside a single package. As an apparatus targeting the above-described compactness and multiple pin features, a semiconductor apparatus has been proposed for example in Japanese Laid-Open Patent Publication 6-334098. As shown in FIG. 11 and FIG. 12, this semiconductor apparatus 110 is formed by joining a heat radiation plate 117 and a flexible wiring board 116, joining a package main body 112 composed of a multilayer printed circuit board on the surface opposite that of the joined area of the heat radiation plate 117, and bending back the flexible wiring board 116 that extends to the outside of the package main body 112 and joining this board to the surface side where a cavity 115 in the package main body 112 has been formed. As shown in FIG. 12, a semiconductor apparatus formed in this manner is composed such that heat radiating fins 117a are already attached to the heat radiating board 117, and lead pins are joined as an external connection terminal 118 via the circuit board 116a such as the printed circuit board, to the outer surface of the flexible wiring board 116 joined to the package main body 112.
In addition, among the above-described multi-chip packages in which a plurality of semiconductor chips are arranged within a single package, there are flat MCPs in which the plurality of semiconductor chips are lined up in a planar surface, and stacked MCPs in which the plurality of semiconductor chips are stacked in the direction of thickness. Flat MCPs in which the-semiconductor chips are lined up in a planar surface require a large mounting surface area, and hence contribute little to increasing the compactness of electronic equipment. Consequently, development of stacked MCPs in which the semiconductor chips are stacked is being conducted in abundance. As an example, there is technology, such as that disclosed in Japanese Laid-Open Patent Publication 6-204399 and Japanese Laid-Open Patent Publication 8-167630, wherein modules are formed by stacking semiconductor chips vertically after sealing such inside a package, and electrical connection between packages is accomplished using via holes and through holes.
However, in the aforementioned semiconductor apparatus of Japanese Laid-Open Patent Publication 6-334098, assembly is complicated because the apparatus is produced joining the package main body 112, in which a cavity 115 is formed and printed boards having a set wiring pattern formed in advance are stacked up to one side of the flexible printed circuit board 116, creating the problem that the result effectively cannot be made compact.
In addition, with a conventional stacked MCP, it is necessary to form via holes and through holes for accomplishing inter-layer connection in order to electrically connect the semiconductor chips and the wiring board, and hence production processes, such as positioning between layers, processing holes, filling holes with a conductor or plating process, are difficult. Consequently, apparatuses have been proposed in which the semiconductor chips are mounted on an insulating film tape in which copper wiring has been provided without using complex production processes such as for via holes and through holes and the like, and the stacked semiconductor chips are electrically connected, for example Japanese Laid-Open Patent Publication 8-167630. In a semiconductor module comprising at least a single semiconductor chip, a substrate on which such is mounted, and wiring electrically connected to said semiconductor chip formed on this substrate, multi-layering is accomplished by folding the above-described substrate, and the space between layers of said substrate are adhered by an adhesion means. In addition, between the folded layers, a heat dispersion board is placed and heat is dispersed. In addition, it is noted that between the folded layers, a board is placed to secure rigidity, the rigidity of the semiconductor module is increased, rising of solder balls through deformations such as flexing is prevented, and the electrical connection between the semiconductor module and the wiring board is made certain. However, in that disclosure, the board is folded from the area of the ridge folding lines and the valley folding lines to accomplish multi-layering, and furthermore, a semiconductor chip is placed within the same empty space as the valley folding lines area, while within this empty space, the active surfaces of the semiconductor chips are positioned facing each other. Consequently, the substrate is such that with the ridge folding lines, enlargement becomes necessary because of the fear that breaking of the wiring or the like could arise if the bending radius is reduced, and in addition, because these ridge folding lines exist in a plurality of locations, the semiconductor module becomes thick. Moreover, the heat generated from the mutually facing semiconductor chips acts on each, and furthermore, the temperature is raised and abnormal operation occurs in the semiconductor chips, and eventually, abnormalities are caused in the semiconductor modules as a result of this. In particular, when the active surfaces of the semiconductor chips are placed in positions facing each other, this heat acts mutually and abnormal operations occur easily. For this reason, in said disclosure a heat dispersion board is placed between the semiconductor chips and the heat is dispersed, but because this is placed in contact with the active surfaces, there is no change in the mutual action of the heat generated by the semiconductor chips via the heat dispersion board, the temperature does not go down enough, so the temperature rises and abnormal operation is caused in the semiconductor chip, while the problem also remains that the package is large.
In consideration of the foregoing, it is an objective of the present invention to provide a semiconductor apparatus wherein a semiconductor chip and an interposer are both placed besides each other on a carrier tape, and in which the electrical properties are improved using short wiring with a wiring pattern substantially symmetric with respect to the semiconductor chip, production is easy, and which is compact with improved heat radiation. In addition, it is another objective of this invention to obtain a semiconductor apparatus in which the used surface area is reduced using carrier tape on which electronic parts are mounted, and accompanying that, the exterior dimensions of the package as a whole can be reduced, the mounting area can be shrunk, the ease of operation and productivity can be improved and the production cost can be lowered.
In order to accomplish the above objectives, the semiconductor apparatus of the present invention is such that a semiconductor chip connected electrically to wiring formed on a carrier tape, and an interposer provided on the carrier tape and near said semiconductor chip, are provided beside each other, the semiconductor chip and the interposer are overlapped by bending the carrier tape so that the semiconductor chip positioned in the center is enclosed, and the result is covered by a molding.
The present invention as configured in this manner has a carrier tape material with substantially the same length in the left-right direction of the diagrams, and/or the front-back direction, with respect to the semiconductor chip placed in the center, and consequently it is possible to shorten the length of the wiring pattern and improve the electrical properties. In addition, it suffices to bend the short carrier tape symmetric left-to-right the same way on the left and the right, making production easy.
In addition, the semiconductor apparatus of the present invention can have a composition such that a plurality of semiconductor chips arranged in a row and electrically connected to wiring form on the carrier tape, and interposers on the carrier tape and also on both the top and bottom sides of the semiconductor chip arranged in the center thereof, are provided next to each other, and multi-layering is accomplished by bending the carrier tape and overlapping the interposer on one surface of the semiconductor chip in the center and the other semiconductor chips on the other surface, and covering the result with molding resin.
The present invention as configured in this manner has, as noted above, a carrier tape material with substantially the same length in the left-right direction of the diagram with respect to the semiconductor chip placed in the center, and consequently it is possible to shorten the length of the wiring pattern and improve the electrical properties. In addition, it is possible to make the apparatus more compact because the carrier tape and the interposer are positioned adjacent to each other.
In addition, the semiconductor apparatus of the present invention may have the tape material interposer placed on the carrier tape adjacent to the semiconductor chips arranged in a row, while an external connection terminal is provided to the interposer.
The present invention as configured in this manner has a tape material interposer placed on the carrier tape adjacent to the semiconductor chips arranged in a row, while an external connection terminal is provided to the interposer, and consequently, the external connection terminal area is reinforced by the interposer, making the cost cheaper and improving with the wiring of a single layer.
In addition, the semiconductor apparatus of the present invention may be multi-layered by overlapping the active surfaces of the semiconductor chips in the top to bottom direction so as to not face each other.
The present invention as configured in this manner can be configured with the active surfaces of the semiconductor chips not facing each other while the semiconductor chips are overlapped and covered with molding resin, and consequently, the semiconductor chips are not placed on a surface with the active surfaces thereof mutually facing, the heat generated from the active surfaces does not mutually work together to raise the heat, and increases in the temperature of the semiconductor chips are reduced. Consequently, abnormal operation does not occur in the semiconductor chip, and the semiconductor module operates properly.
In addition, the semiconductor apparatus of the present invention may also have no carrier tape between the overlapping semiconductor chips.
The present invention as configured in this manner is such that the gap between the stacked semiconductor chips can be reduced by the amount of the carrier tape that has been omitted, making it possible to reduce the thickness of the semiconductor module. In addition, because the carrier tape, which has a poor heat transfer ratio, is not positioned there, the heat radiation of the semiconductor chips improves and the temperature does not rise much, so it is possible to prevent the occurrence of abnormal operations.